A symbolic-simulation approach to the timing verification of interacting FSMs

作者: A.J. Daga , W.P. Birmingham

DOI: 10.1109/ICCD.1995.528927

关键词:

摘要: A timing verifier that scales to verify complex sequential circuits, modeled in terms of interacting FSMs, while rejecting false and combinational paths has, so far, not been developed. We present an algorithm for this purpose. The inherently modular nature interactions among allow a highly efficient symbolic simulation verification methodology. Experimental results illustrate methodology's ability scale, providing accurate results.

参考文章(8)
Zvi Kohavi, Niraj K. Jha, Switching and Finite Automata Theory ,(2010)
M.A. Riepe, J.P. Marques Silva, K.A. Sakallah, R.B. Brown, Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation international conference on computer design. pp. 361- 364 ,(1993) , 10.1109/ICCD.1993.393352
S. Devadas, K. Keutzer, S. Malik, A. Wang, Certified timing verification and the transition delay of a logic circuit IEEE Transactions on Very Large Scale Integration Systems. ,vol. 2, pp. 333- 342 ,(1994) , 10.1109/92.311642
Bryant, Graph-Based Algorithms for Boolean Function Manipulation IEEE Transactions on Computers. ,vol. 35, pp. 677- 691 ,(1986) , 10.1109/TC.1986.1676819
Ajay J. Daga, William P. Birmingham, The Minimization and Decomposition of Interface State Machines design automation conference. pp. 120- 125 ,(1994) , 10.1145/196244.196301
D. H. Du, S. H. Yen, S. Ghanta, On the General False Path Problem in Timing Analysis design automation conference. pp. 555- 560 ,(1989) , 10.1145/74382.74475
Anurag P. Gupta, Daniel P. Siewiorek, Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-based Designs design automation conference. pp. 113- 119 ,(1994) , 10.1145/196244.196299
Derek L. Beatty, Randal E. Bryant, Formally Verifying a Microprocessor Using a Simulation Methodology design automation conference. pp. 596- 602 ,(1994) , 10.1145/196244.196575