作者: A.J. Daga , W.P. Birmingham
关键词:
摘要: A timing verifier that scales to verify complex sequential circuits, modeled in terms of interacting FSMs, while rejecting false and combinational paths has, so far, not been developed. We present an algorithm for this purpose. The inherently modular nature interactions among allow a highly efficient symbolic simulation verification methodology. Experimental results illustrate methodology's ability scale, providing accurate results.