作者: Hiroshi Hasegawa
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摘要: An N-bit A/D converter comprises 2 N cells connected in cascade, wherein the start cell receives an input analog signal and each performs a determination operation to produce signal. Each sample hold circuit, comparator, subtracter. The circuit samples value from first received previous holds value. comparator compares with reference subtracter subtracts subtrahend second which is by next cell. output of as above-mentioned same cascade-connected are controlled timing clocks so perform pipeline such that produces when