作者: Naoya C , Koichi c
DOI:
关键词: Comparator 、 Cascade 、 Subtractor 、 Analog signal 、 Settling time 、 A d converter 、 Electrical engineering 、 Signal 、 Least significant bit 、 Electronic engineering 、 Computer science
摘要: A cascade A/D converter that has shorter settling time and enables high-speed operation is provided. comprises fundamental constituent elements cascaded in plural stages, each element comprising a first comparator for inputting an analog input signal, D/A converting output of the to signal again, subtractor subtracting from comprising: second every least significant bit near transition point comparator; arithmetic operating unit generating upper bits based on interpolating lower comparator.