A pipelined 9-stage video-rate analog-to-digital converter
作者： S.H. Lewis , H.S. Fetterman , G.F. Gross , R. Ramachandran , T.R. Viswanathan
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摘要: The authors describe a nine-stage, pipelined, video-rate, analog-to-digital converter (ADC) in 0.9- mu m CMOS technology. At conversion rate of 20 Msamples/s, the has 10-b resolution, 56-dB signal-to-noise-and-distortion ratio (SNDR) with 100-kHz input, and 54-dB SNDR 5-MHz input. It occupies 9.3 mm/sup 2/ dissipates 300 mW. key innovation this ADC is improved correction algorithm, which requires one fewer comparator per stage than used traditional architectures. >
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