Recent progress in integration of III?V nanowire transistors on Si substrate by selective-area growth

摘要: We report on the recent progress in electronic applications using III–V nanowires (NWs) Si substrates selective-area growth method. This method could align vertical NWs under specific conditions. Detailed studies of NW/Si heterointerface showed possibility achieving coherent regardless misfit dislocations III–V/Si heterojunction. The grown were utilized for high performance field-effect transistors (FETs). Furthermore, heterointerfaces with fewer provided us a unique band discontinuity new functionality that can be used application tunnel diodes and FETs. These demonstrations open door to approach creating low power switches as building-blocks future nanometre-scaled circuits platforms.