On estimating bounds of the quiescent current for I/sub DDQ/ testing
作者： A. Ferre , J. Figueras
DOI: 10.1109/VTEST.1996.510843
关键词:
摘要: The quiescent current (I/sub DDQ/) consumed by an IC is a good indicator of the presence large defects. However, effectiveness I/sub DDQ/ testing requires appropriate discriminability defective and defect-free currents hence it becomes necessary to estimate involved in order design sensing circuitry. In this work, we present method non-defective consumption based on hierarchical approach using layout (device), electrical (cell) logic (circuit) information. maximum obtained with technique ATPG. results show that proposed gives for small circuits. For circuits, heuristics find lower upper bounds are presented. Uncertainty margins than 15% have been found circuits experimented on.
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