Novel sidewall interconnection using perpendicular circuit die with non-solder bumps for 3D chip stack
作者： Sun-Rak Kim , Il Kim , Jae Hak Lee , Seung S. Lee
DOI: 10.1109/ECTC.2012.6248994
关键词:
摘要: A new sidewall interconnection using perpendicular circuit die is implemented in this work; device can be applied to fabrication of chip stacks. Experiments were conducted by stacking four chips each having a thickness 200μm; the configuration pad on test similar that memory chip. The for fabricated successfully dicing wafer. Vertical was made thermo-compression bonding die. quality stack examined through SEM images. images show interconnections successfully. high-temperature/high-humidity stacked at 85°/85%RH lasting 1000 hours used investigate mechanical reliability packages. It found maintained their integrity. strength all interfaces remained as high they before test. electrical resistance comparable obtained wire bonding.
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