Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding

摘要: One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a assembly are potentially much shorter than 2D configuration, allowing for faster system speed and lower power consumption. However, it extremely important use cost-effective process technologies practical use. Therefore, our study, we propose basic concept interconnecting stacked chips with TSVs technology. The principal feature ldquomechanical-caulkingrdquo technique, which has been used widely the mechanical-engineering field, enabling interconnections between chips. This makes possible interconnect them by only applying compressive force at room temperature. paper presents results obtained mechanical-caulking connections temperature accomplished manufacturing prototype of chip-stacked package TSV interconnections. A 3D-SiP composed an existing MCU, interposer, SDRAM was also manufactured. customized design, assuming needs be introduced achieve SiO2 etching turn around time (TATs) high yields more 99%.