Generation of optimal universal logic modules
作者： R. Drechsler , W. Gunther
DOI: 10.1109/EURMIC.1999.794451
关键词:
摘要: The realization of efficient universal logic modules (ULMs) is a challenging topic in circuit design. goal to find representation that allows realize as many Boolean functions possible by permutation inputs or phase assignment. In this paper an exact algorithm for finding minimal ULM presented. approach parametrisized several ways, e.g. the user can define library gates and specify should be realized within module. Starting from input description enumerates all generates area and/or delay netlist. Experimental results are given show efficiency approach.
sci-hub.se 参考文章(4)
Robert K. Brayton, Alberto Sangiovanni-Vincentelli, Rajeev Murgai, Logic Synthesis for Field-Programmable Gate Arrays ,(1995)
Chih-chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin, Universal logic gate for FPGA design international conference on computer aided design. pp. 164- 168 ,(1994) , 10.5555/191326.191393
Z. Zilic, Z.G. Vranesic, Using decision diagrams to design ULMs for FPGAs IEEE Transactions on Computers. ,vol. 47, pp. 971- 982 ,(1998) , 10.1109/12.713316
E.S. Davidson, An Algorithm for NAND Decomposition Under Network Constraints IEEE Transactions on Computers. ,vol. 18, pp. 1098- 1109 ,(1969) , 10.1109/T-C.1969.222593