Logic Synthesis for Field-Programmable Gate Arrays

作者： Robert K. Brayton , Alberto Sangiovanni-Vincentelli , Rajeev Murgai

DOI:

关键词: Sequential logic 、 Logic family 、 Programmable logic device 、 Programmable logic array 、 Logic synthesis 、 Theoretical computer science 、 Simple programmable logic device 、 Computer science 、 Computational logic 、 Logic optimization 、 Arithmetic

摘要: Preface. Part I: Introduction. 1. 2. Background. II: Look-up table (LUT) architectures. 3. Mapping computational logic. 4. Logic optimization. 5. Complexity issues. 6. sequential 7. Performance directed synthesis. III: Multiplexor-based 8. combinational IV: Conclusions. 10. References. Index.

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Logic Synthesis for Field-Programmable Gate Arrays

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Logic Synthesis for Field-Programmable Gate Arrays

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