Technology mapping of LUT based FPGAs for delay optimisation

摘要: This paper presents a new LUT based technology mapping approach for delay optimisation. To optimise the circuit after layout, wire delays are taken into account in our model. In addition, an effective is proposed to trade-off CLB and so as minimise whole delay. The achieved two phases, area optimisation followed by reduction techniques. Based on standard set of benchmark examples, experimental results PPR layout have shown that outperforms state-of-the-art approaches.