Simultaneous block and I/O buffer floorplanning for flip-chip design

摘要: The flip-chip package gives the highest chip density of any packaging method to support pad-limited ASIC design. One most important characteristics designs is that input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce floorplanning problem for design and formulate it as assigning positions first-stage/last-stage blocks so path length between bump balls well delay skew paths are simultaneously minimized. We then present hierarchical solve problem. cluster block its corresponding reduce size. Then, go into iterations alternating interacting global optimization step partitioning step. places based on simulated annealing using B*-tree representation minimize given cost function. dissects two subregions, divided groups in respective subregions. steps repeat until each subregion contains at number blocks, defined by ratio total area area. At last, refine floorplan perturbing different Compared with floorplanner alone, our more efficient obtains significantly better results, an average only 51.8% obtained set real industrial provided leading companies.