Incremental I/O planning with white space redistribution for flip-chip design

摘要: The flip-chip package gives the highest chip density of any packaging method to support pad-limited ASIC design. One most important characteristics designs is that input/output buffers could be placed anywhere inside a chip. We need focus on not only assignment I/O bumps, but also cost for placing buffer blocks into In this paper, we first introduce incremental floorplanning problem design in which white space packings can optimized favor insertion buffers. So initial packing results migrated matched up with pattern without sacrificing much previous optimization original designs. then present min flow based algorithms optimize terms interconnect cost. experimental have shown our algorithm improve wirelength by about 20% while Power/Groud(P/G) and signal are distributed more evenly.