Self-synchronizing scrambler

摘要: A self-synchronizing scrambler for high bit rates has a number of stages supplied in parallel with bits signal to be scrambled, each stage having series-connected pair modulo-2 adders, and at least one shift register. selected the may include an additional register depending upon p total n registers scrambler. The two is n-p following 2 p-n. For suppressing short periods, further adder can connected between original inverting periods.