Method and system for analyzing quiescent power plane current (IDDQ) test data in very-large scale integrated (VLSI) circuits
作者： Anne Elizabeth Gattiker
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摘要: A method and system for analyzing quiescent power plane current test data in a very large scale integrated (VLSI) circuit provides diagnostic information improved IDDQ testing detecting manufacturing defects VLSI device. set of values is collected over vectors group devices. Values that are detected as corresponding to activated (e.g., shorts) discarded from the checked correlation between remaining ostensibly defect-free devices (or alternatively vectors) do not correlate set. Then, regression generated each vector at selected reference (excepting vector). Next, device normalized by estimating an expected value device's measured value. cross-correlation check performed determine whether measurements represents good measurements. New defect previously potentially reclaimed. The above regression, normalization discard procedure repeated until non-defect stable can be categorized into discrete categories. may used identifying diagnosing defective and/or acceptability determined values.
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