作者: Thomas E. Westberg
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摘要: An intelligent cache memory system and associated method for reducing a central processing unit (CPU) idle time. The performs prefetches based on data fetching characteristics of the CPU. includes control logic, first second memory, each having number lines, tag array, entries corresponding to lines. comprise tags valid bits. array further interest In addition their traditional functions, bits, in conjunction with are used track history For read cycle, logic returns being fetched by CPU from either or main memory. Additionally, initiates prefetch updates conditionally. also stored whereas prefetched Prefetch is conditioned history, while update where requested fetched. As result, time reduced performance improved.