System and method for high voltage stress testing plurality of parallel units
作者： L Rene' Graves , Joseph Milton Yehle , Xu Gao
DOI:
关键词:
摘要: A system has a chip mounting board and docking board. The can be loaded with test samples in low voltage environment then transported to high environment. connected the allows testing of multiple parallel. disconnected from back unload tested samples.
lens.org 参考文章(12)
Michael Russell Uy Gonzales, Louie Que Hermosura, Teck Seng Eng, Efficient method of retesting integrated circuits ,(2013)
Mike Chen, Ramon S. Co, David Sun, Manufacturing method for partially-good memory modules with defect table in EEPROM ,(2007)
Satwinder Malhi, Oh K. Kwon, Shivaling S. Mahant-Shetti, Flip-chip test socket adaptor and method ,(1989)
Keith Robinson, Load board socket adapter and interface method ,(2002)
Robert W. Rollings, James W. Cassarly, Frank C. Youngfleish, Connector mounting for integrated circuit chip packages ,(1981)
Douglas S. Ondricek, David V. Pedersen, Method for mounting an electronic component ,(1999)
Siew Kng Tan, Samuel Syn Soo Lim, Reusable carrier for burn-in/testing on non packaged die ,(1993)
Shiang-Ruei Su, Liang-Chen Lin, Chia-Wei Tu, Test chip, test board and reliability testing method ,(2012)
Young Ho Kim, Hwa Jin Jeong, Testing apparatus for non-packaged semiconductor chip ,(1997)