Method and structure for testing embedded cores based system-on-a-chip
作者： Rochit Rajsuman , Hiroaki Yamoto
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摘要: A method of testing embedded cores in an integrated circuit chip having a microprocessor core, memory core and other functional therein. The includes the steps of; forming plurality registers chip, by executing its instructions multiple times with pseudo random data evaluating results comparing simulation results, applying test program to generate pattern response function specific thereto resultant output signals cores.
google.co.uk 参考文章(9)
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