Spider: a high-speed network interconnect

摘要: SGI's Spider chip-Scalable, Pipelined Interconnect for Distributed Endpoint Routing-create a scalable, short-range network delivering hundreds of gigabytes per second in bandwidth to large configurations. Individual chips sustain 4.8-Gbyte/s switching rate, connecting each other and endpoints across cables up 5 meters length. By very high bandwidth-thousands times higher than standard Ethernet-at low latencies, is ideal CPU interconnect applications, high-end switches, or high-performance graphics interconnects. The chip design drew on the principles computer communications architecture. Isolation between physical, data link, message layers led well-structured that transportable more easily verified nonlayered solution. Because implements all hardware, latency low. Thus, we could realize benefits layering without sacrificing performance.