SMEFF: A scalable memory extension fabric for FPGA

摘要: In resource-constrained FPGA systems, off-chip memory plays an important role in both prototype verification and acceleration systems for big data. As the scale of applications become increasingly large complex, data to be processed grows exponentially. contrast, FPGAs provide limited capacity bandwidth, severely limiting performance systems. Furthermore, movement is expected a dominant consumer energy, thus inefficient between different DRAM modules also incurs significant energy penalties. This paper proposes practical design: A Scalable Memory Extension Fabric (SMEFF), which asynchronous access mechanism exploits cascaded technology solve problem bandwidth. SMEFF uses two key technologies achieve bandwidth improvements, shrink latency overhead movement-the first FPGA-based high-speed serial bus build multi-level fabric instead traditional parallel signal integrity problem. The second module (M-To-M) DMA technology, reduces modules. We implement on demonstrate feasibility our approach. Experimental results show that provides 5x increase up 3.6x improvement compared state-of-the-art outperforms PCIe-based M-TO-M's obtains 3x reduction, average 21.1% 61.1% reduction increases More importantly, architecture opportunities design scalable, cost-effective subsystems.