Reevaluating Data Stall Time with the Consideration of Data Access Concurrency

摘要: Data access delay has become the prominent performance bottleneck of high-end computing systems. The key to reducing data in system design is diminish stall time. Memory locality and concurrency are two essential factors influencing modern memory However, existing studies time rarely focus on utilizing because impact overall not well understood. In this study, a pair novel models, L-C model for combined effort P-M effect pure miss time, presented. models provide new understanding directions optimization. Based these summary table advanced cache optimizations It 38 entries contributed by while only 21 locality, which shows value concurrency. their associated results opportunities introduced study important necessary future data-centric architecture algorithm