Smart memory based synchronization controller for a multi-threaded multiprocessor SoC

摘要: A memory interface for use with a multiprocess system having gating memory, the associating one or more access methods each of plurality locations wherein returns particular method location responsive to instruction relating location, including: request storage storing concurrent instructions locations, issued from an associated independent thread context; arbiter, coupled storage, selecting apply memory; and controller, for: in storage; initiating application selected by arbiter receiving communication context instruction.