Microprocessor with on-chip cache memory with lower power consumption

作者: Hidechica Kishigami , Kiyotaka Sasai , Tohru Sasaki

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摘要: A microprocessor with on-cache memory and an address translation buffer in which it further comprises first second flip-flop circuits for indicating hit or miss the tag field of cache storing X Y sections a target data exists. Access to is carried out prior access memory, thereby preventing when occurs field, thus decreasing power consumption.

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