作者: I. K. Hetherington , P. Kusulas
DOI: 10.1002/J.1538-7305.1983.TB04391.X
关键词:
摘要: The memory system supplied with the 3B20D Processor provides a high-reliability, high-performance, main-frame for use by Central Control and Input/Output system. is designed using collection of high-speed, static dynamic devices appropriate logic controllers. In addition to providing basic on-line storage program text data, hardware assistance virtual-to-physical address translation, access protection, resource arbitration, performance enhancement utilizing high-speed cache memory. technology used in implementing these functions includes state-of-the-art 64K random TTL-compatible gate-array integrated circuits.