Hardware architecture design for explicit model predictive control

摘要: Solutions to constrained linear and hybrid model predictive control (MPC) can be explicitly characterized in terms of piecewise (PWL) state feedback control. A PWL controller is pre-computed using parametric programming, the exact explicit MPC implementation corresponds evaluation a function unit. It has recently been shown that such boosted by binary search tree data structures. We report digital hardware architecture design results for this type control, show solutions implemented standard field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) with about 20 kGates leading computation times around one microsecond per typical applications. This facilitates small-scale industrial consumer electronics applications are fast sampling low production cost, as mechatronics, MEMS, rotating machinery, power electronics, acoustics.