A partitioning flow for accelerating applications in processor-FPGA systems

摘要: This paper presents a hardware/software partitioning flow for improving performance in systems-on- chip comprised by processor and Field Programmable Gate Array. Speedups are achieved executing critical software parts on the reconfigurable FPGA logic. A generic hybrid system architecture is considered methodology. The uses an automated analysis process at basic-block level detecting application parts. Two different instances of platform five real-world applications used experiments. analytical experimentation illustrates that speedup ranges from 1.3 to 3.7 relative all solution.