Improving Software Performance with Configurable Logic

作者: Jason Villarreal , Dinesh Suresh , Greg Stitt , Frank Vahid , Walid Najjar

DOI: 10.1023/A:1020359206122

关键词:

摘要: We examine the energy and performance benefits that can be obtained by re-mapping frequently executed loops from a microprocessor to reconfigurable logic. present design flow finds critical software automatically manually re-implements these inconfigurable logic implementing them in SA-C, C language variation supportinga dataflow computation model designed specify map DSP applicationsonto apply this on several examples fromthe MediaBench benchmark suite report improvements.

参考文章(18)
Asawaree Kalavade, Edward A. Lee, The extended partitioning problem: hardware/software mapping, scheduling, and implementation-bin selection Design Automation for Embedded Systems. ,vol. 2, pp. 125- 163 ,(1997) , 10.1023/A:1008872518365
Walid A. Najjar, Bruce A. Draper, A. P. Wim Böhm, Robert Rinker, Jeffrey Hammes, A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems. parallel and distributed processing techniques and applications. ,(2000)
W Böhm, Jeffrey Hammes, B Draper, Monica Chawathe, Charlie Ross, Robert Rinker, W Najjar, None, Mapping a Single Assignment Programming Language to Reconfigurable Systems The Journal of Supercomputing. ,vol. 21, pp. 117- 130 ,(2002) , 10.1023/A:1013623303037
Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alexa Doboli, System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search Design Automation for Embedded Systems. ,vol. 2, pp. 5- 32 ,(1997) , 10.1023/A:1008857008151
W. Najjar, B. Draper, R. Rinker, C. Ross, M. Chawathe, A.P.W. Bohm, J. Hammes, One-Step Compilation of Image Processing Applications to FPGAs field-programmable custom computing machines. pp. 209- 218 ,(2001) , 10.1109/FCCM.2001.32
J. Hammes, A.P.W. Bohm, C. Ross, M. Chawathe, B. Draper, R. Rinker, W. Najjar, Loop fusion and temporal common subexpression elimination in window-based loops international parallel and distributed processing symposium. pp. 142- ,(2001) , 10.1109/IPDPS.2001.925126
M.B. Gokhale, J.M. Stone, NAPA C: compiling for a hybrid RISC/FPGA architecture field-programmable custom computing machines. pp. 126- 135 ,(1998) , 10.1109/FPGA.1998.707890
Tony Givargis, Frank Vahid, Jörg Henkel, System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip international conference on computer aided design. pp. 25- 30 ,(2001) , 10.5555/603095.603101
P.M. Athanas, H.F. Silverman, Processor reconfiguration through instruction-set metamorphosis IEEE Computer. ,vol. 26, pp. 11- 18 ,(1993) , 10.1109/2.204677
T. Givargis, F. Vahid, J. Henkel, System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip IEEE Transactions on Very Large Scale Integration Systems. ,vol. 10, pp. 416- 422 ,(2002) , 10.1109/TVLSI.2002.807764