Method and apparatus for testing memory
作者： James A. Gasbarro , Victor E. Lee , Lawrence Lai
DOI:
关键词:
摘要: A method and apparatus for testing DRAM is described. The causes the pins to be reconfigured provide a direct path between memory core pins. This reconfiguration allows “seen” without probing also faster simpler with more traditional protocol. provides several options further increase speed. These include an internal block compare noise option. performs parallel bit by comparison of read data contents write buffer generates error signal if mismatch occurs. option simulates that can occur during normal mode operation does not testing.
lens.org 参考文章(7)
Duc Pham-Minh, Pierre-Albert Comte, Mariano Bona, Methods and test platforms for developing an application-specific integrated circuit ,(1995)
Patrick P. Fasang, Walter F. Bridgewater, Built-in self test for integrated circuit memory ,(1990)
Alexander Perez, Ralph Warren Haines, Kent B. Waterson, David S. Weinman, Brian J. Marley, James A. Colgan, Michael J. Shay, John R. Gunther, Dan Craig O'neill, Daniel R. Herrington, Jianhua Helen Pang, Stephen C. Pries, Robert J. Divivier, Mario Nemirovsky, Integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitration ,(1996)
Shigehiro Kuge, Semiconductor memory devices having a built-in test function ,(1997)
Thomas M. Surrette, Neil P. Raftery, Jonathan F. Churchill, Jeyakumar Shanmugam, Colin J. Hendry, Mark A. Finn, Cathal G. Phelan, Ashish Pancholy, Scan path circuitry including a programmable delay circuit ,(1997)
Steve P. Kornachuk, Scott T. Becker, Craig R. Silver, Programmable universal test interface for testing memories with different test methodologies ,(1998)
Kenichi Fujisaki, Memory testing device for multiported DRAMs ,(1993)