Cache coherency sequencing implementation and adaptive LLC access priority control for CMP
作者： Zhong-ning Cai , Krishnakanth V. Sistla , Jeffrey D. Gilbert , Yen-Cheng Liu
DOI:
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摘要: A method and apparatus for cache coherency sequencing implementation an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level among multiple internal CMP cores, snoops external snoops. Another implementing in multi-core system.
google.com.mx 参考文章(24)
John Carmine Pescatore, SDRAM L3 cache using speculative loads with command aborts to lower latency ,(1998)
Felix Pinai, Manhtien Phan, Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs ,(1997)
Krishnakanth Sistla, Yen-Cheng Liu, George Cai, Cache filtering using core indicators ,(2004)
Leslie Zsohar, Thomas G. Leete, Abdolreza Naeini, Michael Kent Blanchard, M. Nicholas Matelan, Dennis Kyle Smith, Jacob Hsu, Multicomputer digital processing system ,(1985)
Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Decentralized global coherency management in a multi-node computer system ,(2001)
Patrick Francis Dutton, Steven Lee Gregor, Hehching Harry Li, Storage subsystem including an error correcting cache and means for performing memory to memory transfers ,(1999)
Tracy Garrett Drysdale, Scott P Bobholz, Method and apparatus for communicating between processing entities in a multi-processor ,(2001)
Robert J. Safranek, Kai Cheng, Partially inclusive snoop filter ,(2002)
Doron Orenstien, Ronny Ronen, Distribution of processing activity across processing hardware based on power consumption considerations ,(2001)
Manohar K. Prabhu, Preemptive write back controller ,(2001)