Steered frequency phase locked loop

摘要: A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like normal locked (PLL) and locks to the input signal, frequency uses reference influence effectively confines output of SFPLL be in range frequencies close frequency. The is chosen very signal it desired lock to. detector (10), (22), first second gain components (12, 24), first, third filter (14, 18, 26), summer (16) voltage controlled oscillator (VCO) (20). By judicious choice gains loops can designed so which will confined an arbitrarily small region around ( omega 'r). Applications include demodulation CW modulation systems timing recovery from NRZ data. Three advantages are equal or when no present, frequency, instabilities VCO reduced.