Hysteresis behaviour of top-down fabricated ZnO nanowire transistors
作者： S. M. Sultan , P. Ashburn , R. Ismail , H. M. H. Chong
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摘要: Top-down Zinc Oxide (ZnO) nanowire FETs have been fabricated using conventional photolithography, ZnO atomic layer deposition (ALD) and dry etching. This paper investigates the hysteresis characteristics of these transistors at different gate bias sweep rates. Hysteresis is a measure charge trapping detrapping activities on surface. Maximum width obtained for this top-down NWFET device when measured in air was 2.2 V. value smaller compared to other bottom up devices which indicates better interface quality between nanowire/SiO2 interface. Subsequently, an important feature order produce reliable platform electronic applications particularly sensing applications.
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