Design challenges of technology scaling

摘要: Scaling advanced CMOS technology to the next generation improves performance, increases transistor density, and reduces power consumption. Technology scaling typically has three main goals: 1) reduce gate delay by 30%, resulting in an increase operating frequency of about 43%; 2) double density; 3) energy per transition 65%, saving 50% (at a 43% frequency). These are not ad hoc goals; rather, they follow theory. This article looks closely at past trends how well microprocessor products have met these goals. It also projects challenges that lie ahead if continue. analysis uses data from various Intel microprocessors; however, this study is equally applicable other types logic designs. Is process meeting goals predicted theory? An through successive generations helps identify potential limiters scaling, integration.