Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools

摘要: By adding a few logic gates and one or two modeling flip-flops to the circuit under test (CUT), we create detection diagnostic automatic pattern generation (ATPG) model of transition delay faults usable by conventional single stuck-at fault generator. Given pair, ATPG can either find an exclusive prove equivalence pair. Our work offers advantages over existing work. First, diagnosis pair be modeled in only instead four time-frames CUT. Second, generated launch off capture (LOC) shift (LOS) mode for full-scan sequential circuit. Third, proposed models expanded into time frames facilitate use combinational tools, though with lower complexity than was possible before. As result, percentage distinguished pairs is larger system more time-efficient.