An interchip Power Line Communication
作者： Paulo Marcos Pinto , Tales Cleber Pimenta , Robson Luiz Moreno , Odilon Dutra , Rodrigo da Silva Braga
DOI: 10.1109/ISICIR.2016.7829743
关键词:
摘要: Dense wired networks, such as ultra-dense EEG network, comprised of 256 or 512 electrodes for temporal and spatial analysis the brain, demand a large amount wiring. Instead using pair wires power supply additional wiring communication, use Power Line Communications (PLC) allows communication in single wires. In this project, we propose transceiver (transmitter receiver) 0.18µm CMOS technology, 1.8V operating at 10 MHz. Simulations conducted on CADENCE (Virtuoso Analog Design Environment L Editing) demonstrate circuit is capable transmitting receiving data properly.
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