Mixed-V/sub th/ (MVT) CMOS circuit design methodology for low power applications

摘要: Dual threshold technique has been proposed to reduce leakage power in low voltage and circuits by applying a high some transistors non-critical paths, while low-threshold is used critical path(s) maintain the performance. Mixed-V/sub th/ (MVT) static CMOS design allows different thresholds within logic gate, thereby increasing number of compared gate-level dual technique. In this paper, methodology for MVT circuit presented. Different schemes are considered three algorithms transistor-level assignment under performance constraints. Results indicate that can provide about 20% more reduction corresponding