The effect of LUT and cluster size on deep-submicron FPGA performance and density

摘要: In this paper, we revisit the field-programmable gate-array (FPGA) architectural issue of effect logic block functionality on FPGA performance and density. particular, in context lookup table, cluster-based island-style FPGAs (Betz et al. 1997) look at table (LUT) size cluster (number LUTs per cluster) speed density an FPGA. We use a fully timing-driven experimental flow 1997), (Marquardt, 1999) which set benchmark circuits are synthesized into different Rose, 1997, 1998) architectures, contain groups flip-flops. Across all architectures with LUT sizes range 2 to 7 inputs, from 1 10 LUTs, have experimentally determined relationship between number inputs required for as function (K) (N). Second, contrary previous results, shown that clustering small (sizes 3) produces better area results than what was presented past. However, our also show these is significantly worse (by almost factor 2) larger LUTs. Hence, measured by area-delay product, or performance, would be bad choice. Also, discovered 5 6 produce much were previously believed. Finally, 4 3-10 provides best product