Tile-based modular routing resources for high density programmable logic device

摘要: Signal routing resource tiles that can be manipulated as circuit "cells" in they readily characterized and implemented on a programmable logic device, e.g., field gate array (FPGA). In one embodiment, vertical placement horizontal are provided. Routing resources may selectively added areas of the device determined to prone high signal congestion, central portions array, along perimeter. The additional simplify for complex functions increase utilization configurable blocks (CLBs) forming array. positioned within any position horizontally or vertically CLB Specifically, either core chip periphery with each tile providing connections existing (e.g., input/output ports) CLBs. A corner is also provided permits interconnection between tiles. modular nature so number an their based array's particular need resources, have one, two more associated row column CLBs where congestion typically encountered. Each present invention include plurality switch matrices, buffers, other active gates facilitate routing.