Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

摘要: A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation networks in a symmetrical structure. The includes direct connections for each configurable logic block to eight neighbors, including adjacent blocks next blocks. Also, uncommitted lines which are driven by outputs but not committed through inputs any specific block. Rather, other segments interconnect. also staggered switching matrices at intersections horizontal vertical buses Repowering buffers that both directions associated bidirectional interconnect, include bypass path. provides control from off chip, input/output structures or all array.