A new fast algorithm for 8/spl times/8 2-D DCT and its VLSI implementation
作者： Mao Tian , Guang-Jun Li , Qi-Zong Peng
DOI: 10.1109/IWVDVT.2005.1504580
关键词:
摘要: Due to the importance of discrete cosine transform (DCT) in field coding images, various algorithms and architectures for real-time 2-D DCT processor designs have been proposed. In this paper we present a new fast algorithm 8/spl times/8 based on partial sum its corresponding hardware architecture VLSI realization. The costs fewest multipliers theory system is serial-in serial-out system. Theoretical proof simulation results FPGA devices show efficiency algorithm. kernel regular with lower complexity performs high throughput.
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