Efficient Implementation of 2-D FCT with Reduced Memory Access for Programmable DSPs

摘要: In this paper, we present a novel memory access reduction scheme (MARS) for two-dimension fast cosine transform (2-D FCT). It targets programmable DSPs with high memory-access latency. reduces the number of accesses by: 1) reducing weighting factors and 2) combining butterflies in vector-radix 2-D FCT pruning diagram from two stages to one stage an efficient structure. Hardware platform based on general purpose processor is used verify effectiveness proposed method implementation. Experimental results validate benefits reduced access, less clock cycle fewer space compared conventional