On digit-recurrence division implementations for field programmable gate arrays
作者： M.E. Louie , M.D. Ercegovac
DOI: 10.1109/ARITH.1993.378091
关键词:
摘要: The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic-intensive programs with the benefits of custom hardware but without the high cost of custom silicon …
sci-hub.se 参考文章(11)
Charles E. Leiserson, Flavio M. Rose, James B. Saxe, Optimizing Synchronous Circuitry by Retiming (Preliminary Version) Springer, Berlin, Heidelberg. pp. 87- 116 ,(1983) , 10.1007/978-3-642-95432-0_7
Milos D. Ercegovac, On-Line Arithmetic: An Overview 28th Annual Technical Symposium. ,vol. 0495, pp. 86- 93 ,(1984) , 10.1117/12.944012
M. Shand, P. Bertin, J. Vuillemin, Hardware speedups in long integer multiplication ACM Sigarch Computer Architecture News. ,vol. 19, pp. 106- 113 ,(1991) , 10.1145/121956.121968
J. Paul Roth, R. M. Karp, Minimization over Boolean graphs Ibm Journal of Research and Development. ,vol. 6, pp. 227- 238 ,(1962) , 10.1147/RD.62.0227
James E. Robertson, A New Class of Digital Division Methods Ire Transactions on Electronic Computers. ,vol. 7, pp. 218- 222 ,(1958) , 10.1109/TEC.1958.5222579
M. D. Ercegovac, T. Lang, A division algorithm with prediction of quotient digits symposium on computer arithmetic. pp. 51- 56 ,(1985) , 10.1109/ARITH.1985.6158946
M.E. Louie, M.D. Ercegovac, Mapping division algorithms to field programmable gate arrays asilomar conference on signals, systems and computers. pp. 371- 375 ,(1992) , 10.1109/ACSSC.1992.269172
Robert J. Francis, Jonathan Rose, Kevin Chung, Chortle: a technology mapping program for lookup table-based field programmable gate arrays design automation conference. pp. 613- 619 ,(1990) , 10.1145/123186.123418
P. Bertin, D. Roncin, J. Vuillemin, Programmable active memories: a performance assessment Proceedings of the First Heinz Nixdorf Symposium on Parallel Architectures and Their Efficient Use. pp. 119- 130 ,(1992) , 10.1007/3-540-56731-3_12
Robert Francis, Jonathan Rose, Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs design automation conference. pp. 227- 233 ,(1991) , 10.1145/127601.127670