FPGA implementation of modified radix 2 SRT division algorithm
作者： A.A. Ibrahem , H. Elsimary , A.E. Salama
DOI: 10.1109/MWSCAS.2003.1562561
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摘要: The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefits custom hardware but without high cost silicon implementations. In this paper, we present adaptation modified radix 2 division algorithm by Cquillan, et al. (1993) for lookup table based FPGAs implementation. For scheme, result digits and residuals are computed concurrently computations in adjacent rows overlapped. implementation has been done Xilinx technology FPGA-Advantage CAD tools.
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