Stacked ferroelectric memory cell
作者： William L. Larson
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摘要: A ferroelectric memory cell has an FET covered by insulation layer and a capacitor located thereover. An interconnect couples upper plate of the to source/drain transistor. In method forming cells, after transistor is fabricated, bottom electrode dielectric are established, but top not added until further over windows opened in it. One window for another one region FET.
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