A memory system design framework

摘要: As CPU cores become building blocks, we see a great expansion in the types of on-chip memory systems proposed for CMPs. Unfortunately, designing cache and protocol controllers to support these is complex, their concurrency latency characteristics significantly affect performance any CMP. To address this problem, paper presents microarchitecture framework controllers, which can aid generating RTL new systems. The consists three pipelined engines' request-tracking, state-manipulation, data movement' are programmed implement higher-level model. This approach simplifies design verification CMP by decomposing model into sequences state manipulations. Moreover, implementing itself produces polymorphic system.To validate approach, implemented scalable, flexible silicon. system was then disparate models' coherent shared memory, streams transactional memory. Measured overheads seem promising. Our generates with less than 20% compared an ideal controller zero internal latency. Even overhead directly fully programmable modest. While it did double controller's area, amortized effective area grew roughly 7%.