A programmable memory controller for the DDRx interfacing standards

摘要: Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing resource constraints on system performance. A promising way improving versatility efficiency these is make them programmable—a proven technique that has seen wide use in other control tasks, ranging from DMA scheduling NAND Flash directory control. Unfortunately, stringent latency throughput requirements modern DDRx devices have rendered such programmability largely impractical, confining fixed-function hardware.This article presents instruction set architecture (ISA) hardware implementation PARDIS, a programmable controller can meet performance high-speed interface. The proposed evaluated by mapping previously refresh algorithms onto PARDIS. Simulation results show average PARDIS comes within 8p for each techniques; moreover, enabling application-specific optimizations, improves 6 17p reduces energy 9 22p over four existing controllers.