Data processor generating jump target address of a jump instruction in parallel with decoding of the instruction
作者： Toyohiko Yoshida , Masahito Matsuo
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摘要: A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory stores instructions; decoding 112 decodes the fetched 111; execution executes on basis of result by 112; program counter (DPC) 29 holds address being decoded in and branch target calculation 1 is connected to 29, adds value displacement field transferred transfers addition 111, so that jump can be processed efficiently pipeline processing.
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