Dual floating gate programmable read only memory cell structure and method for its fabrication and operation

作者: Fernando Gonzalez , Francis L. Bensistant

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摘要: A flash memory cell in the form of a transistor capable storing multi-bit binary data is disclosed. pair floating gates are provided beneath control gate. The gate connected to word line while active doped regions (source and drain regions) respective digit lines. separately charged read out by controlling voltages applied charges decoded into value. One or both has side insulator which connects through conductor an associated region thereby forming capacitor across between This facilitates operation as cell. Methods fabricating operating it also

参考文章(20)
Robert Hasbun, Greg Atwood, Steven Wells, Mark Bauer, Mark Christopherson, Albert Fazio, Error management processes for flash eeprom memory arrays ,(1995)
Frank Chiou, Tony Wang, Lenvis Liu, Chong-Jen Huang, Hsin-Huei Chen, Method for manufacturing flash memory device with dual floating gates and two bits per cell ,(2000)
Mong-Song Liang, Ruei-Ling Lin, Di-Son Kuo, Ching-Hsiang Hsu, Multi-level, split-gate, flash memory cell and method of manufacture thereof ,(1996)
Kenji Kohda, Tsuyoshi Toyama, Nobuaki Ando, Kenji Noguchi, Shinichi Kobayashi, Non-volatile semiconductor memory device with facility of storing tri-level data ,(1988)
B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, A. Modelli, Multilevel flash cells and their trade-offs international electron devices meeting. pp. 169- 172 ,(1996) , 10.1109/IEDM.1996.553147
Harish Narandas Kotecha, Iii Francis Walter Wiedman, Jr. Wendell Phillips Noble, Electrically alterable double dense memory ,(1981)