Random access analog memory for early vision

作者: E. Franchi , M. Tartagni , R. Guerrieri , G. Baccarani

DOI: 10.1109/4.142610

关键词:

摘要: An analog frame buffer suitable for early-vision processing is described. It has been fabricated using digital 1.6- mu m CMOS technology. A novel architecture presented to compensate the effect of parameter mismatch. The chip stores an image a time 1/30 s with equivalent precision more than 6 b. array size 32*32 and cell dimension 30.8 m*40 m. Power consumption below 30 mW requires bias supply 5 V. >

参考文章(16)
Harald Philipp, Optical motion sensor ,(1987)
D. Renshaw, P.B. Denyer, G. Wang, M. Lu, ASIC image sensors international symposium on circuits and systems. pp. 3038- 3041 ,(1990) , 10.1109/ISCAS.1990.112652
G. Wegmann, E.A. Vittoz, F. Rahali, Charge injection in analog MOS switches IEEE Journal of Solid-State Circuits. ,vol. 22, pp. 1091- 1097 ,(1987) , 10.1109/JSSC.1987.1052859
R. Castello, D.D. Caviglia, M. Franciotta, F. Montecchi, Selfrefreshing analogue memory cell for variable synaptic weights Electronics Letters. ,vol. 27, pp. 1871- 1873 ,(1991) , 10.1049/EL:19911161
Carver Mead, Analog VLSI and Neural Systems ,(1989)
A. Agranat, A. Yariv, Semiparallel microelectronic implementation of neural network models using CCD technology Electronics Letters. ,vol. 23, pp. 580- 581 ,(1987) , 10.1049/EL:19870416
Y Tsividis, S Satyanarayana, None, Analogue circuits for variable-synapse electronic neural networks Electronics Letters. ,vol. 23, pp. 1313- 1314 ,(1987) , 10.1049/EL:19870908
D.L. Standley, An object position and orientation IC with embedded imager international solid-state circuits conference. ,vol. 26, pp. 1853- 1859 ,(1991) , 10.1109/4.104177
K. Dejhan, N. Demassieux, O. Colavin, A. Galisson, A. Artieri, F. Jutand, Design of a low-power 32 K CMOS programmable delay-line memory IEEE Journal of Solid-state Circuits. ,vol. 25, pp. 234- 238 ,(1990) , 10.1109/4.50309
M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, Matching properties of MOS transistors IEEE Journal of Solid-state Circuits. ,vol. 24, pp. 1433- 1439 ,(1989) , 10.1109/JSSC.1989.572629