Multilevel Power Estimation Of VLSI Circuits Using Efficient Algorithms

摘要: New and complex systems are being implemented using highly advanced Electronic Design Automation (EDA) tools. As the complexity increases day by day, dissipation of power has emerged as one very important design constraints. Now low designs not only used in small size applications like cell phones handheld devices but also high-performance computing applications. Embedded memories have been extensively modern SOC designs. In order to estimate consumption entire correctly, an accurate memory model is needed. However, commonly commercial EDA tools too simple accurately. For digital circuits, building their models a popular approach without detailed circuit information. literature, most built with lookup tables. tables may become infeasible for large circuits because table would increase exponentially meet accuracy requirement. This thesis involves two parts. first part it uses Synopsys measurement together use synthesis extraction determine consumed various macros at different levels abstraction including Register Transfer Level (RTL), gate transistor level. general, can be concluded that level goes down depending on tool used. second novel modeling neural networks learn relationship between input/output characteristic vector during simulation developed. Our such this circuits. Using structure, still high they automatically consider non-linear distributions. Unlike characterization process traditional approaches, our straightforward. More importantly, estimation does require any transistor-level or gate-level description The experimental results shown estimations efficient test sequences wide range input