VLSI architecture for fast 2D discrete orthonormal wavelet transform

摘要: The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low coarser resolution. It decomposes signal or an image into localized contributions multiscale analysis. In this paper, we present parallel pipelined VLSI array architecture 2D dyadic separable DWT. data is partitioned non-overlapping groups of rows. All rows in partition processed parallel, consecutive partitions pipelined. Moreover, multiple levels computed the same pipeline, DWT problems can be also. whole computation requires single scan array. Thus, it suitable on-line real-time applications. For anN×N image, anm-level $$\tfrac{{N^2 }}{{2_q }} + 2^{m - 1} (2p 3)$$ units on processor costing no more than $$\tfrac{8}{3}(C_m C_u )p(p 2q)$$ , whereq size,p length corresponding 1D filters,Cm andCa costs multiplier adder respectively, unit multiplication addition. Forq=N ? m, computing reduces to $$\frac{N}{2}$$ . When large number pipelined, about }}$$ per problem.